Intel Xeon E5-2658 V2

CPE Details

Intel Xeon E5-2658 V2
intel
xeon_e5-2658_v2
-
2017-02-28
18h49 +00:00
2023-09-27
18h23 +00:00
CPE NVD
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CPE Name: cpe:2.3:h:intel:xeon_e5-2658_v2:-:*:*:*:*:*:*:*

Informations

Vendor

intel

Product

xeon_e5-2658_v2

Version

-

Related CVE

Open and find in CVE List

CVE ID Publié Description Score Gravité
CVE-2022-24436 2022-06-15 18h08 +00:00 Observable behavioral in power management throttling for some Intel(R) Processors may allow an authenticated user to potentially enable information disclosure via network access.
6.5
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CVE-2020-0551 2020-03-12 20h04 +00:00 Load value injection in some Intel(R) Processors utilizing speculative execution may allow an authenticated user to potentially enable information disclosure via a side channel with local access. The list of affected products is provided in intel-sa-00334: https://www.intel.com/content/www/us/en/security-center/advisory/intel-sa-00334.html
5.6
Moyen
CVE-2020-0550 2020-03-12 20h02 +00:00 Improper data forwarding in some data cache for some Intel(R) Processors may allow an authenticated user to potentially enable information disclosure via local access. The list of affected products is provided in intel-sa-00330: https://www.intel.com/content/www/us/en/security-center/advisory/intel-sa-00330.html
5.6
Moyen
CVE-2019-0151 2019-11-14 18h07 +00:00 Insufficient memory protection in Intel(R) TXT for certain Intel(R) Core Processors and Intel(R) Xeon(R) Processors may allow a privileged user to potentially enable escalation of privilege via local access.
6.7
Moyen
CVE-2019-11184 2019-09-16 13h59 +00:00 A race condition in specific microprocessors using Intel (R) DDIO cache allocation and RDMA may allow an authenticated user to potentially enable partial information disclosure via adjacent access.
4.8
Moyen
CVE-2017-5925 2017-02-27 06h25 +00:00 Page table walks conducted by the MMU during virtual to physical address translation leave a trace in the last level cache of modern Intel processors. By performing a side-channel attack on the MMU operations, it is possible to leak data and code pointers from JavaScript, breaking ASLR.
7.5
Haute
CVE-2017-5926 2017-02-27 06h25 +00:00 Page table walks conducted by the MMU during virtual to physical address translation leave a trace in the last level cache of modern AMD processors. By performing a side-channel attack on the MMU operations, it is possible to leak data and code pointers from JavaScript, breaking ASLR.
7.5
Haute
CVE-2017-5927 2017-02-27 06h25 +00:00 Page table walks conducted by the MMU during virtual to physical address translation leave a trace in the last level cache of modern ARM processors. By performing a side-channel attack on the MMU operations, it is possible to leak data and code pointers from JavaScript, breaking ASLR.
7.5
Haute