CPE Details
Advanced Micro Devices (AMD) EPYC 7573X Firmware MilanPI 1.0.0.8
milanpi_1.0.0.8
2023-01-18
10h59 +00:00
10h59 +00:00
2023-01-25
05h04 +00:00
05h04 +00:00
Alerte pour un CPE
Stay informed of any changes for a specific CPE.
CPE Name: cpe:2.3:o:amd:epyc_7573x_firmware:milanpi_1.0.0.8:*:*:*:*:*:*:*
Informations
Vendor
amdProduct
epyc_7573x_firmwareVersion
milanpi_1.0.0.8Related CVE
| CVE ID | Published | Description | Score | Severity |
|---|---|---|---|---|
| Improper re-initialization of IOMMU during the DRTM event may permit an untrusted platform configuration to persist, allowing an attacker to read or modify hypervisor memory, potentially resulting in loss of confidentiality, integrity, and availability. | 10 |
Critical |
||
| IOMMU improperly handles certain special address ranges with invalid device table entries (DTEs), which may allow an attacker with privileges and a compromised Hypervisor to induce DTE faults to bypass RMP checks in SEV-SNP, potentially leading to a loss of guest integrity. | 6 |
Medium |
||
| Improper restriction of write operations in SNP firmware could allow a malicious hypervisor to potentially overwrite a guest's memory or UMC seed resulting in loss of confidentiality and integrity. | 7.9 |
High |
||
| Improper input validation in SEV-SNP could allow a malicious hypervisor to read or overwrite guest memory potentially leading to data leakage or data corruption. | 7.9 |
High |
||
| Improper restriction of write operations in SNP firmware could allow a malicious hypervisor to overwrite a guest's UMC seed potentially allowing reading of memory from a decommissioned guest. | 6 |
Medium |
||
| Due to a code bug in Secure_TSC, SEV firmware may allow an attacker with high privileges to cause a guest to observe an incorrect TSC when Secure TSC is enabled potentially resulting in a loss of guest integrity. | 4.9 |
Medium |
||
| Failure to initialize memory in SEV Firmware may allow a privileged attacker to access stale data from other guests. | 6 |
Medium |
||
| Improper or unexpected behavior of the INVD instruction in some AMD CPUs may allow an attacker with a malicious hypervisor to affect cache line write-back behavior of the CPU leading to a potential loss of guest virtual machine (VM) memory integrity. | 6.5 |
Medium |
||
| Improper address validation in ASP with SNP enabled may potentially allow an attacker to compromise guest memory integrity. | 7.5 |
High |
||
| SMM configuration may not be immutable, as intended, when SNP is enabled resulting in a potential limited loss of guest memory integrity. | 5.3 |
Medium |
||
| Failure to validate the value in APCB may allow a privileged attacker to tamper with the APCB token to force an out-of-bounds memory read potentially resulting in a denial of service. | 4.9 |
Medium |
||
| Insufficient DRAM address validation in System Management Unit (SMU) may allow an attacker to read/write from/to an invalid DRAM address, potentially resulting in denial-of-service. | 7.5 |
High |
||
| A side channel vulnerability on some of the AMD CPUs may allow an attacker to influence the return address prediction. This may result in speculative execution at an attacker-controlled address, potentially leading to information disclosure. | 4.7 |
Medium |
||
| Insufficient address validation, may allow an attacker with a compromised ABL and UApp to corrupt sensitive memory locations potentially resulting in a loss of integrity or availability. | 7.1 |
High |
||
| Insufficient input validation of mailbox data in the SMU may allow an attacker to coerce the SMU to corrupt SMRAM, potentially leading to a loss of integrity and privilege escalation. | 9.8 |
Critical |
2025©
tesweb SA
