Intel Core i7-4500u

CPE Details

Intel Core i7-4500u
intel
core_i7-4500u
-
2017-02-28
18h49 +00:00
2023-09-26
11h34 +00:00
CPE NVD
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CPE Name: cpe:2.3:h:intel:core_i7-4500u:-:*:*:*:*:*:*:*

Informations

Vendor

intel

Product

core_i7-4500u

Version

-

Related CVE

Open and find in CVE List

CVE ID Published Description Score Severity
CVE-2022-24436 2022-06-15 18h08 +00:00 Observable behavioral in power management throttling for some Intel(R) Processors may allow an authenticated user to potentially enable information disclosure via network access.
6.5
Medium
CVE-2020-0543 2020-06-15 11h55 +00:00 Incomplete cleanup from specific special register read operations in some Intel(R) Processors may allow an authenticated user to potentially enable information disclosure via local access.
5.5
Medium
CVE-2020-0551 2020-03-12 20h04 +00:00 Load value injection in some Intel(R) Processors utilizing speculative execution may allow an authenticated user to potentially enable information disclosure via a side channel with local access. The list of affected products is provided in intel-sa-00334: https://www.intel.com/content/www/us/en/security-center/advisory/intel-sa-00334.html
5.6
Medium
CVE-2020-0550 2020-03-12 20h02 +00:00 Improper data forwarding in some data cache for some Intel(R) Processors may allow an authenticated user to potentially enable information disclosure via local access. The list of affected products is provided in intel-sa-00330: https://www.intel.com/content/www/us/en/security-center/advisory/intel-sa-00330.html
5.6
Medium
CVE-2017-5925 2017-02-27 06h25 +00:00 Page table walks conducted by the MMU during virtual to physical address translation leave a trace in the last level cache of modern Intel processors. By performing a side-channel attack on the MMU operations, it is possible to leak data and code pointers from JavaScript, breaking ASLR.
7.5
High
CVE-2017-5926 2017-02-27 06h25 +00:00 Page table walks conducted by the MMU during virtual to physical address translation leave a trace in the last level cache of modern AMD processors. By performing a side-channel attack on the MMU operations, it is possible to leak data and code pointers from JavaScript, breaking ASLR.
7.5
High
CVE-2017-5927 2017-02-27 06h25 +00:00 Page table walks conducted by the MMU during virtual to physical address translation leave a trace in the last level cache of modern ARM processors. By performing a side-channel attack on the MMU operations, it is possible to leak data and code pointers from JavaScript, breaking ASLR.
7.5
High