CPE Details
Advanced Micro Devices (AMD) EPYC 7303P Firmware MilanPI 1.0.0.A
milanpi_1.0.0.a
2023-11-22
16h07 +00:00
16h07 +00:00
2023-11-22
16h07 +00:00
16h07 +00:00
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CPE Name: cpe:2.3:o:amd:epyc_7303p_firmware:milanpi_1.0.0.a:*:*:*:*:*:*:*
Informations
Vendor
amdProduct
epyc_7303p_firmwareVersion
milanpi_1.0.0.aRelated CVE
| CVE ID | Published | Description | Score | Severity |
|---|---|---|---|---|
| Improper re-initialization of IOMMU during the DRTM event may permit an untrusted platform configuration to persist, allowing an attacker to read or modify hypervisor memory, potentially resulting in loss of confidentiality, integrity, and availability. | 10 |
Critical |
||
| IOMMU improperly handles certain special address ranges with invalid device table entries (DTEs), which may allow an attacker with privileges and a compromised Hypervisor to induce DTE faults to bypass RMP checks in SEV-SNP, potentially leading to a loss of guest integrity. | 6 |
Medium |
||
| Improper restriction of write operations in SNP firmware could allow a malicious hypervisor to potentially overwrite a guest's memory or UMC seed resulting in loss of confidentiality and integrity. | 7.9 |
High |
||
| Improper input validation in SEV-SNP could allow a malicious hypervisor to read or overwrite guest memory potentially leading to data leakage or data corruption. | 7.9 |
High |
||
| Improper restriction of write operations in SNP firmware could allow a malicious hypervisor to overwrite a guest's UMC seed potentially allowing reading of memory from a decommissioned guest. | 6 |
Medium |
||
| Due to a code bug in Secure_TSC, SEV firmware may allow an attacker with high privileges to cause a guest to observe an incorrect TSC when Secure TSC is enabled potentially resulting in a loss of guest integrity. | 4.9 |
Medium |
||
| Failure to initialize memory in SEV Firmware may allow a privileged attacker to access stale data from other guests. | 6 |
Medium |
||
| Improper or unexpected behavior of the INVD instruction in some AMD CPUs may allow an attacker with a malicious hypervisor to affect cache line write-back behavior of the CPU leading to a potential loss of guest virtual machine (VM) memory integrity. | 6.5 |
Medium |
||
| Improper address validation in ASP with SNP enabled may potentially allow an attacker to compromise guest memory integrity. | 7.5 |
High |
||
| Insufficient DRAM address validation in System Management Unit (SMU) may allow an attacker to read/write from/to an invalid DRAM address, potentially resulting in denial-of-service. | 7.5 |
High |
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