Reserved bits are labeled as such so they can be allocated for a later purpose. They are not to do anything in the current design. However, designers might want to use these bits to debug or control/configure a future capability to help minimize time to market (TTM). If the logic being controlled by these bits is still enabled in production, an adversary could use the logic to induce unwanted/unsupported behavior in the hardware.
Scope | Impact | Likelihood |
---|---|---|
Confidentiality Integrity Availability Access Control Accountability Authentication Authorization Non-Repudiation | Varies by Context Note: This type of weakness all depends on the capabilities of the logic being controlled or configured by the reserved bits. |
Include a feature to disable reserved bits.
Any writes to these reserve bits are blocked (e.g., ignored, access-protected, etc.), or an exception can be asserted.
CAPEC-ID | Attack Pattern Name |
---|---|
CAPEC-121 | Exploit Non-Production Interfaces An adversary exploits a sample, demonstration, test, or debug interface that is unintentionally enabled on a production system, with the goal of gleaning information or leveraging functionality that would otherwise be unavailable. |
Name | Organization | Date | Date release | Version |
---|---|---|---|---|
Brent Sherman | Intel Corporation | 4.0 |
Name | Organization | Date | Comment |
---|---|---|---|
CWE Content Team | MITRE | updated Related_Attack_Patterns | |
CWE Content Team | MITRE | updated Potential_Mitigations | |
CWE Content Team | MITRE | updated Demonstrative_Examples | |
CWE Content Team | MITRE | updated Demonstrative_Examples | |
CWE Content Team | MITRE | updated Relationships | |
CWE Content Team | MITRE | updated Mapping_Notes |