CWE-1233
Alerte pour un CWE
Security-Sensitive Hardware Controls with Missing Lock Bit Protection
Extended Description
Integrated circuits and hardware intellectual properties (IPs) might provide device configuration controls that need to be programmed after device power reset by a trusted firmware or software module, commonly set by BIOS/bootloader. After reset, there can be an expectation that the controls cannot be used to perform any further modification. This behavior is commonly implemented using a trusted lock bit, which can be set to disable writes to a protected set of registers or address regions. The lock protection is intended to prevent modification of certain system configuration (e.g., memory/memory protection unit configuration).
However, if the lock bit does not effectively write-protect all system registers or controls that could modify the protected system configuration, then an adversary may be able to use software to access the registers/controls and modify the protected hardware configuration.
Informations
Modes Of Introduction
Architecture and Design : Such issues could be introduced during hardware architecture and design and identified later during Testing or System Configuration phases.Implementation : Such issues could be introduced during implementation and identified later during Testing or System Configuration phases.
Applicable Platforms
Language
Class: Not Language-Specific (Undetermined)Operating Systems
Class: Not OS-Specific (Undetermined)Architectures
Class: Not Architecture-Specific (Undetermined)Technologies
Class: Not Technology-Specific (Undetermined)Common Consequences
| Scope | Impact | Likelihood |
|---|---|---|
| Access Control | Modify Memory Note: System Configuration protected by the lock bit can be modified even when the lock is set. |
Observed Examples
| Reference | Description |
|---|---|
| Certain servers leave a write protection lock bit unset after boot, potentially allowing modification of parts of flash memory. | |
| Chain: chipset has a race condition (CWE-362) between when an interrupt handler detects an attempt to write-enable the BIOS (in violation of the lock bit), and when the handler resets the write-enable bit back to 0, allowing attackers to issue BIOS writes during the timing window [REF-1237]. |
Potential Mitigations
Phases : Architecture and Design // Implementation // Testing- Security lock bit protections must be reviewed for design inconsistency and common weaknesses.
- Security lock programming flow and lock properties must be tested in pre-silicon and post-silicon testing.
Detection Methods
Manual Analysis
Set the lock bit. Attempt to modify the information protected by the lock bit. If the information is changed, implement a design fix. Retest. Also, attempt to indirectly clear the lock bit or bypass it.Effectiveness : High
Vulnerability Mapping Notes
Rationale : This CWE entry is at the Base level of abstraction, which is a preferred level of abstraction for mapping to the root causes of vulnerabilities.Comments : Carefully read both the name and description to ensure that this mapping is an appropriate fit. Do not try to 'force' a mapping to a lower-level Base/Variant simply to comply with this preferred level of abstraction.
Related Attack Patterns
| CAPEC-ID | Attack Pattern Name |
|---|---|
| CAPEC-176 | Configuration/Environment Manipulation An attacker manipulates files or settings external to a target application which affect the behavior of that application. For example, many applications use external configuration files and libraries - modification of these entities or otherwise affecting the application's ability to use them would constitute a configuration/environment manipulation attack. |
| CAPEC-680 | Exploitation of Improperly Controlled Registers An adversary exploits missing or incorrectly configured access control within registers to read/write data that is not meant to be obtained or modified by a user. |
References
REF-1237
Intel BIOS locking mechanism contains race condition that enables write protection bypassCERT Coordination Center.
https://www.kb.cert.org/vuls/id/766164/
Submission
| Name | Organization | Date | Date Release | Version |
|---|---|---|---|---|
| Arun Kanuparthi, Hareesh Khattri, Parbati Kumar Manna, Narasimha Kumar V Mangipudi | Intel Corporation | 4.0 |
Modifications
| Name | Organization | Date | Comment |
|---|---|---|---|
| CWE Content Team | MITRE | updated Related_Attack_Patterns | |
| CWE Content Team | MITRE | updated Maintenance_Notes | |
| CWE Content Team | MITRE | updated Demonstrative_Examples, Description, Detection_Factors, Maintenance_Notes, Name, Observed_Examples, Potential_Mitigations, References, Relationships, Weakness_Ordinalities | |
| CWE Content Team | MITRE | updated Related_Attack_Patterns, Relationships | |
| CWE Content Team | MITRE | updated Relationships | |
| CWE Content Team | MITRE | updated Mapping_Notes |
