Modes Of Introduction
Architecture and Design
Implementation
Applicable Platforms
Language
Class: Not Language-Specific (Undetermined)
Operating Systems
Class: Not OS-Specific (Undetermined)
Architectures
Class: Not Architecture-Specific (Undetermined)
Technologies
Name: Bus/Interface Hardware (Undetermined)
Class: Not Technology-Specific (Undetermined)
Common Consequences
| Scope |
Impact |
Likelihood |
Confidentiality Integrity Access Control Authorization | Bypass Protection Mechanism, Read Memory, Modify Memory | Medium |
Observed Examples
| References |
Description |
| Attacker can modify MCHBAR register to overlap with an attacker-controlled region, which modification prevents the SENTER instruction from properly applying VT-d protection while a Measured Launch Environment is being launched. |
Potential Mitigations
Phases : Architecture and Design
When architecting the address map of the chip, ensure that protected and unprotected ranges are isolated and do not overlap. When designing, ensure that ranges hardcoded in Register-Transfer Level (RTL) do not overlap.
Phases : Implementation
Ranges configured by firmware should not overlap. If overlaps are mandatory because of constraints such as a limited number of registers, then ensure that no assets are present in the overlapped portion.
Phases : Testing
Validate mitigation actions with robust testing.
Detection Methods
Automated Dynamic Analysis
Review address map in specification to see if there are any overlapping ranges.
Effectiveness : High
Manual Static Analysis
Negative testing of access control on overlapped ranges.
Effectiveness : High
Vulnerability Mapping Notes
Justification : This CWE entry is at the Base level of abstraction, which is a preferred level of abstraction for mapping to the root causes of vulnerabilities.
Comment : Carefully read both the name and description to ensure that this mapping is an appropriate fit. Do not try to 'force' a mapping to a lower-level Base/Variant simply to comply with this preferred level of abstraction.
Related Attack Patterns
| CAPEC-ID |
Attack Pattern Name |
| CAPEC-456 |
Infected Memory
An adversary inserts malicious logic into memory enabling them to achieve a negative impact. This logic is often hidden from the user of the system and works behind the scenes to achieve negative impacts. This pattern of attack focuses on systems already fielded and used in operation as opposed to systems that are still under development and part of the supply chain. |
| CAPEC-679 |
Exploitation of Improperly Configured or Implemented Memory Protections
|
Notes
As of CWE 4.6, CWE-1260 and CWE-1316 are siblings under view 1000, but CWE-1260 might be a parent of CWE-1316. More analysis is warranted.
References
REF-1137
BARing the System - New vulnerabilities in Coreboot & UEFI-based Systems
Yuriy Bulygin, Oleksandr Bazhaniuk, Andrew Furtak, John Loucaides, Mikhail Gorobets.
https://www.c7zero.info/stuff/REConBrussels2017_BARing_the_system.pdf
Submission
| Name |
Organization |
Date |
Date release |
Version |
| Arun Kanuparthi, Hareesh Khattri, Parbati Kumar Manna |
Intel Corporation |
2020-06-01 +00:00 |
2020-12-10 +00:00 |
4.3 |
Modifications
| Name |
Organization |
Date |
Comment |
| CWE Content Team |
MITRE |
2021-10-28 +00:00 |
updated Maintenance_Notes |
| CWE Content Team |
MITRE |
2022-04-28 +00:00 |
updated Applicable_Platforms, Related_Attack_Patterns |
| CWE Content Team |
MITRE |
2022-06-28 +00:00 |
updated Applicable_Platforms |
| CWE Content Team |
MITRE |
2022-10-13 +00:00 |
updated References |
| CWE Content Team |
MITRE |
2023-01-31 +00:00 |
updated Related_Attack_Patterns |
| CWE Content Team |
MITRE |
2023-04-27 +00:00 |
updated Relationships |
| CWE Content Team |
MITRE |
2023-06-29 +00:00 |
updated Mapping_Notes |
| CWE Content Team |
MITRE |
2025-12-11 +00:00 |
updated Weakness_Ordinalities |