CWE-1332 Detail

The device is missing or incorrectly implements circuitry or sensors that detect and mitigate the skipping of security-critical CPU instructions when they occur.

The operating conditions of hardware may change in ways that cause unexpected behavior to occur, including the skipping of security-critical CPU instructions. Generally, this can occur due to electrical disturbances or when the device operates outside of its expected conditions.

In practice, application code may contain conditional branches that are security-sensitive (e.g., accepting or rejecting a user-provided password). These conditional branches are typically implemented by a single conditional branch instruction in the program binary which, if skipped, may lead to effectively flipping the branch condition - i.e., causing the wrong security-sensitive branch to be taken. This affects processes such as firmware authentication, password verification, and other security-sensitive decision points.

Attackers can use fault injection techniques to alter the operating conditions of hardware so that security-critical instructions are skipped more frequently or more reliably than they would in a "natural" setting.

Modes Of Introduction

Architecture and Design : Failure to design appropriate countermeasures to common fault injection techniques can manifest this weakness.
Implementation : This weakness can arise if the hardware design incorrectly implements countermeasures to prevent fault injection.

Applicable Platforms

Language

Class: Not Language-Specific (Undetermined)

Operating Systems

Class: Not OS-Specific (Undetermined)

Architectures

Class: Not Architecture-Specific (Undetermined)

Technologies

Class: System on Chip (Undetermined)

Common Consequences

Observed Examples

Potential Mitigations

Phases : Architecture and Design
Design strategies for ensuring safe failure if inputs, such as Vcc, are modified out of acceptable ranges.
Phases : Architecture and Design
Design strategies for ensuring safe behavior if instructions attempt to be skipped.
Phases : Architecture and Design
Identify mission critical secrets that should be wiped if faulting is detected, and design a mechanism to do the deletion.
Phases : Implementation
Add redundancy by performing an operation multiple times, either in space or time, and perform majority voting. Additionally, make conditional instruction timing unpredictable.
Phases : Implementation
Use redundant operations or canaries to detect and respond to faults.
Phases : Implementation
Ensure that fault mitigations are strong enough in practice. For example, a low power detection mechanism that takes 50 clock cycles to trigger at lower voltages may be an insufficient security mechanism if the instruction counter has already progressed with no other CPU activity occurring.

Detection Methods

Automated Static Analysis

This weakness can be found using automated static analysis once a developer has indicated which code paths are critical to protect.
Effectiveness : Moderate

Simulation / Emulation

This weakness can be found using automated dynamic analysis. Both emulation of a CPU with instruction skips, as well as RTL simulation of a CPU IP, can indicate parts of the code that are sensitive to faults due to instruction skips.
Effectiveness : Moderate

Manual Analysis

This weakness can be found using manual (static) analysis. The analyst has security objectives that are matched against the high-level code. This method is less precise than emulation, especially if the analysis is done at the higher level language rather than at assembly level.
Effectiveness : Moderate

Vulnerability Mapping Notes

Justification : This CWE entry is at the Base level of abstraction, which is a preferred level of abstraction for mapping to the root causes of vulnerabilities.
Comment : Carefully read both the name and description to ensure that this mapping is an appropriate fit. Do not try to 'force' a mapping to a lower-level Base/Variant simply to comply with this preferred level of abstraction.

Related Attack Patterns

References

REF-1161

An In-depth and Black-box Characterization of the Effects of Clock Glitches on 8-bit MCUs
Josep Balasch, Benedikt Gierlichs, Ingrid Verbauwhede.
https://ieeexplore.ieee.org/document/6076473

REF-1222

Experimental Analysis of the Electromagnetic Instruction Skip Fault Model
Alexandre Menu, Jean-Max Dutertre, Olivier Potin, Jean-Baptiste Rigaud.
https://ieeexplore.ieee.org/document/9081261

REF-1223

Controlling PC on ARM using Fault Injection
Niek Timmers, Albert Spruyt, Marc Witteman.
https://fdtc.deib.polimi.it/FDTC16/shared/FDTC-2016-session_2_1.pdf

REF-1224

Attacking USB Gear with EMFI
Colin O'Flynn.
https://www.totalphase.com/media/pdf/whitepapers/Circuit_Cellar_TP.pdf

REF-1286

On The Susceptibility of Texas Instruments SimpleLink Platform Microcontrollers to Non-Invasive Physical Attacks
Lennert Wouters, Benedikt Gierlichs, Bart Preneel.
https://eprint.iacr.org/2022/328.pdf

Submission

Modifications