CWE-1332 Detail

CWE-1332

Improper Handling of Faults that Lead to Instruction Skips
Stable
2020-12-10
00h00 +00:00
2025-04-03
00h00 +00:00
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Name: Improper Handling of Faults that Lead to Instruction Skips

The device is missing or incorrectly implements circuitry or sensors that detect and mitigate the skipping of security-critical CPU instructions when they occur.

General Informations

Modes Of Introduction

Architecture and Design : Failure to design appropriate countermeasures to common fault injection techniques can manifest this weakness.
Implementation : This weakness can arise if the hardware design incorrectly implements countermeasures to prevent fault injection.

Applicable Platforms

Language

Class: Not Language-Specific (Undetermined)

Operating Systems

Class: Not OS-Specific (Undetermined)

Architectures

Class: Not Architecture-Specific (Undetermined)

Technologies

Class: System on Chip (Undetermined)

Common Consequences

Scope Impact Likelihood
Confidentiality
Integrity
Authentication		Bypass Protection Mechanism, Alter Execution Logic, Unexpected State

Note: Depending on the context, instruction skipping can have a broad range of consequences related to the generic bypassing of security critical code.		High

Observed Examples

References Description

CVE-2019-15894

fault injection attack bypasses the verification mode, potentially allowing arbitrary code execution.

Potential Mitigations

Phases : Architecture and Design
Design strategies for ensuring safe failure if inputs, such as Vcc, are modified out of acceptable ranges.
Phases : Architecture and Design
Design strategies for ensuring safe behavior if instructions attempt to be skipped.
Phases : Architecture and Design
Identify mission critical secrets that should be wiped if faulting is detected, and design a mechanism to do the deletion.
Phases : Implementation
Add redundancy by performing an operation multiple times, either in space or time, and perform majority voting. Additionally, make conditional instruction timing unpredictable.
Phases : Implementation
Use redundant operations or canaries to detect and respond to faults.
Phases : Implementation
Ensure that fault mitigations are strong enough in practice. For example, a low power detection mechanism that takes 50 clock cycles to trigger at lower voltages may be an insufficient security mechanism if the instruction counter has already progressed with no other CPU activity occurring.

Detection Methods

Automated Static Analysis

This weakness can be found using automated static analysis once a developer has indicated which code paths are critical to protect.
Effectiveness : Moderate

Simulation / Emulation

This weakness can be found using automated dynamic analysis. Both emulation of a CPU with instruction skips, as well as RTL simulation of a CPU IP, can indicate parts of the code that are sensitive to faults due to instruction skips.
Effectiveness : Moderate

Manual Analysis

This weakness can be found using manual (static) analysis. The analyst has security objectives that are matched against the high-level code. This method is less precise than emulation, especially if the analysis is done at the higher level language rather than at assembly level.
Effectiveness : Moderate

Vulnerability Mapping Notes

Justification : This CWE entry is at the Base level of abstraction, which is a preferred level of abstraction for mapping to the root causes of vulnerabilities.
Comment : Carefully read both the name and description to ensure that this mapping is an appropriate fit. Do not try to 'force' a mapping to a lower-level Base/Variant simply to comply with this preferred level of abstraction.

Related Attack Patterns

CAPEC-ID Attack Pattern Name
CAPEC-624 Hardware Fault Injection
The adversary uses disruptive signals or events, or alters the physical environment a device operates in, to cause faulty behavior in electronic devices. This can include electromagnetic pulses, laser pulses, clock glitches, ambient temperature extremes, and more. When performed in a controlled manner on devices performing cryptographic operations, this faulty behavior can be exploited to derive secret key information.
CAPEC-625 Mobile Device Fault Injection
Fault injection attacks against mobile devices use disruptive signals or events (e.g. electromagnetic pulses, laser pulses, clock glitches, etc.) to cause faulty behavior. When performed in a controlled manner on devices performing cryptographic operations, this faulty behavior can be exploited to derive secret key information. Although this attack usually requires physical control of the mobile device, it is non-destructive, and the device can be used after the attack without any indication that secret keys were compromised.

References

REF-1161

An In-depth and Black-box Characterization of the Effects of Clock Glitches on 8-bit MCUs
Josep Balasch, Benedikt Gierlichs, Ingrid Verbauwhede.
https://ieeexplore.ieee.org/document/6076473

REF-1222

Experimental Analysis of the Electromagnetic Instruction Skip Fault Model
Alexandre Menu, Jean-Max Dutertre, Olivier Potin, Jean-Baptiste Rigaud.
https://ieeexplore.ieee.org/document/9081261

REF-1223

Controlling PC on ARM using Fault Injection
Niek Timmers, Albert Spruyt, Marc Witteman.
https://fdtc.deib.polimi.it/FDTC16/shared/FDTC-2016-session_2_1.pdf

REF-1224

Attacking USB Gear with EMFI
Colin O'Flynn.
https://www.totalphase.com/media/pdf/whitepapers/Circuit_Cellar_TP.pdf

REF-1286

On The Susceptibility of Texas Instruments SimpleLink Platform Microcontrollers to Non-Invasive Physical Attacks
Lennert Wouters, Benedikt Gierlichs, Bart Preneel.
https://eprint.iacr.org/2022/328.pdf

Submission

Name Organization Date Date release Version
Jasper van Woudenberg Riscure 2020-10-14 +00:00 2020-12-10 +00:00 4.3

Modifications

Name Organization Date Comment
Jasper van Woudenberg Riscure 2021-01-11 +00:00
CWE Content Team MITRE 2021-03-15 +00:00 updated Description, Functional_Areas, Potential_Mitigations, References
CWE Content Team MITRE 2021-10-28 +00:00 updated Demonstrative_Examples, Description, Detection_Factors, Maintenance_Notes, Name, Observed_Examples, Potential_Mitigations, References, Relationships, Weakness_Ordinalities
CWE Content Team MITRE 2022-04-28 +00:00 updated Potential_Mitigations, References, Relationships
CWE Content Team MITRE 2022-06-28 +00:00 updated Relationships
CWE Content Team MITRE 2022-10-13 +00:00 updated References
CWE Content Team MITRE 2023-01-31 +00:00 updated Potential_Mitigations, Related_Attack_Patterns
CWE Content Team MITRE 2023-04-27 +00:00 updated References, Relationships
CWE Content Team MITRE 2023-06-29 +00:00 updated Mapping_Notes
CWE Content Team MITRE 2025-04-03 +00:00 updated Demonstrative_Examples
The information presented on CVE Find originates from several carefully selected reference sources. CVE data is provided by MITRE Corporation and the National Vulnerability Database (NVD). The Known Exploited Vulnerabilities (KEV) catalog is sourced from the Cybersecurity and Infrastructure Security Agency (CISA), while EPSS scores come from FIRST.org. Additionally, data regarding software weaknesses (CWE) and common attack patterns (CAPEC) is maintained by MITRE Corporation, and information on hardware and software configurations (CPE) is provided by the NVD.